MITSUYAMA, Yukio

Associate Professor
CV (Resume, as of July 19, 2017)

School of Systems Engineering, Kochi University of Technology
Tosayamada, Kami, Kochi, 782-8502 JAPAN
Phone: +81-887-57-2114, FAX: +81-887-57-2120
Email: mitsuyama.yukio (at) kochi-tech.ac.jp
Office: A403 (Education and Research Building A)

Research Interest:

• System-on-a-Chip Design
• Reconfigurable Architecture
• Reliable Architecture and its Circuit Design
• Implementation of Media Communication Processing

Representative Publications: Selected Publicaitons

• T. Asada, M. Eguchi, and Y. Mitsuyama, "Performance Variation Measurement on Commercial FPGAs under various Operating Conditions," in IEEE Region 10 Conference (TENCON2016), pp.163--166, Nov. 2016.
• J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," in Proc. International Conference on Field Programmable Logic and Applications (FPL 2016), Aug. 2016.
• M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2015), pp. 14-15, Jan. 2015.
• Y. Mitsuyama, H. Onodera, "Variability and Soft-error Resilience in Dependable VLSI Platform," in Proc. Asian Test Symposium (ATS 2014), pp.45-50, Nov. 2014, (Invited).
• H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518-2529, Dec. 2014.
• H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no.7, pp. 1468-1482, July 2014.
• D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse-grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2165-2178, Dec. 2013.
• D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC 2013), pp. 313-316, Nov. 2013.
• D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
• Y. Mitsuyama, T. Onoye, and H. Onodera "Dependable VLSI Platform Based on Reconfigurable Architecture," Articles of Association of the Institute of Electronics, Information and Communication Engineers (IEICE), vol.96, no.2, pp.95-99, February 2013. (in Japanese)
• T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2012), Aug. 2012.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E94-A, no.12, pp.2545-2553, Dec. 2011.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2011), pp.189-194, Sept. 2011.
• Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Application Design of Multi-Standard Decoder on Media-Centric Reconfigurable Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition), vol.J93-A, no.6, pp.397-413, June 2010.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration," in Proceedings of International Symposium on Quality Electronic Design (ISQED 2010), pp.646-651, Mar. 2010.
• D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2009), pp.186-192, Sept. 2009.
• Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Area-Efficient Reconfigurable Architecture for Media Processing," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp.3651-3662, Dec. 2008.
• Y. Mitsuyama, M. Kimura, T. Onoye, I. Shirakawa, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp.899-906, April 2005.
• Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Embedded Architecture of IEEE802.11i Cipher Algorithms," in Proceedings of IEEE International Symposium on Consumer Electronics (ISCE 2004) , pp. 241-246, Sept. 2004. (Best Paper Award)
• Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "Burst Mode, A New Acceleration Mode for 128-bit Block Ciphers," in Proceedings of Custom Integrated Circuits Conference (CICC 2002), pp. 151-154, May 2002.
• Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfiguration Hardware-Based Cipher,'' IPSJ Journal, vol. 42, no. 4, pp. 958-966, April 2001.
• Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem," Symposium on VLSI Circuits Digest of Technical Papers, pp. 204-205, June 2000.

Academic Degree:

• Ph.D. Information Science and Technology, Osaka University, 2010
• M.Eng. Information Systems Engineering, Osaka University, 2000
• B.Eng. Information Systems Engineering, Osaka University, 1998

Professional Societies:

• Member, Institute of Electrical and Electronics Engineers (IEEE)
• Member, Institute of Electronics, Information and Communication Engineers (IEICE)
• Member, Information Processing Society of Japan (IPSJ)
• Member, Institute of Image Electronics and Engineers of Japan (IIEEJ)

Professional Activities:

• Director (2016, 2017), IEICE Transactions on Fundamentals (Japanese Edition)
• Associate Editors-in-Chief (2017), IPSJ Transactions on System LSI Design Methodology
• Guest Editor (2017), IEICE Transactions on Fundamentals, Special Section on "VLSI Design and CAD Algorithm"
• Guest Associate Editor (2012, 2013, 2015, 2018), IEICE Transactions on Information and Systems, Special Section on "Reconfigurable Systems"
• Finance Chair (2018), International Conference on Field-Programmable Technology (ICFPT)
• Registration Chair (2016), Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
• Registration Chair (2013), International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
• Publicity Chair (2012), International Conference on Embedded Systems and Intelligent Technology (ICESIT)
• Track Co-Chair of "VLSI, Circuits and Systems" (2015) , Program Committee, International Symposium on Communications and Information Technologies (ISCIT)
• Member (2013, 2014), Program Committee, International Conference on Field-Programmable Technology (ICFPT)
• Member (2013, 2014, 2015, 2016, 2017), Program Committee, International Workshop on Computer Systems and Architectures (CSA)