MITSUYAMA, Yukio

Professor
CV (Resume, as of July 19, 2017)

School of Systems Engineering, Kochi University of Technology
Tosayamada, Kami, Kochi, 782-8502 JAPAN
Phone: +81-887-57-2114, FAX: +81-887-57-2120
Email: mitsuyama.yukio (at) kochi-tech.ac.jp
Office: A403 (Education and Research Building A)

Research Interest:

• System-on-a-Chip Design
• HW/SW Co-design
• Reconfigurable Architecture
• Reliable Architecture and its Circuit Design
• Highly Efficient Implementation of Media Processing
• Implementation of Machine Learning Applications

Representative Publications: Selected Publicaitons

• Chavakorn Somjaisuk, Yukio Mitsuyama, and Wang Liao, "Implementation of A2C Algorithm in Reinforcement Learning on CPU-FPGA Embedded System," The 10th Taiwan and Japan Conference on Circuits and Systems (TJCAS 2024), Aug. 2024.
• Thongchai Wayoon, Chavakorn Somjaisuk, Yukio Mitsuyama, and Wnag Liao, "FPGA Acceleration for Image Classification in ROS2 System," The 10th Taiwan and Japan Conference on Circuits and Systems (TJCAS 2024), Aug. 2024.
• M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi, "Via-switch FPGA with Transistor-free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, vol. 61, no. SM0804, June 2022.
• T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, "Impact of Neutron-induced SEU in FPGA CRAM on Image-based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior," IEEE Transactions on Nuclear Science, vol. 69, no. 1, pp.35-42, Jan. 2022.
• W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM," IEEE Transactions on Nuclear Science, vol. 68, no. 6, pp.1228-1234, June 2021.
• Y. Mitsuyama, T. Asada, and M. Eguchi, "Measurement of Variations in FPGAs under Various Load Conditions," IPSJ Transaction on System LSI Design Methodology, vol. 13, pp. 39-41, Feb. 2020.
• R. Yamamoto, Y. Izumi, R. Aono, T. Nagahara, T. Tanaka, W. Liao, and Y. Mitsuyama, "Development of Autonomous Driving System based on Image Recognition using Programmable SoCs," in Proc. International Conference on Field-Programmable Technology (FPT 2021), pp. 1-4, Dec. 2021.
• W . Liao, K. Ito, Y. Mitsuyama and M. Hashimoto, "Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs," in Proc. International Reliability Physics Symposium (IRPS 2020), pp.1-5, April. 2020.
• M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications," IEEE International Solid-State Circuits Conference (ISSCC 2020) Digest of Technical Papers, pp. 502-504, Feb. 2020.
• T. Tanaka, I. Ikeno, R. Tsuruoka, T. Kuchiba, W. Liao, and Y. Mitsuyama, "Development of Autonomous Driving System using Programmable SoCs," in Proc. International Coference on Field-Programmable Technology (FPT 2019), pp. xx-xx, Dec. 2019.
• Y. Mitsuyama, T. Asada, M. Eguchi, "Measurement of Performance Variation of FPGAs under Various Operating Conditions," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), pp. 129-132, July. 2018.
• H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, Vol. 26, No. 12, Dec. 2018.
• H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture," IEEE Embedded Systems Letters, Vol. 10, No. 4, Dec. 2018.
• T. Asada, M. Eguchi, and Y. Mitsuyama, "Performance Variation Measurement on Commercial FPGAs under various Operating Conditions," in IEEE Region 10 Conference (TENCON2016), pp.163--166, Nov. 2016.
• J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," in Proc. International Conference on Field Programmable Logic and Applications (FPL 2016), Aug. 2016.
• M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2015), pp. 14-15, Jan. 2015.
• Y. Mitsuyama, H. Onodera, "Variability and Soft-error Resilience in Dependable VLSI Platform," in Proc. Asian Test Symposium (ATS 2014), pp.45-50, Nov. 2014, (Invited).
• H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518-2529, Dec. 2014.
• H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no.7, pp. 1468-1482, July 2014.
• D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse-grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2165-2178, Dec. 2013.
• D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC 2013), pp. 313-316, Nov. 2013.
• D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
• Y. Mitsuyama, T. Onoye, and H. Onodera "Dependable VLSI Platform Based on Reconfigurable Architecture," Articles of Association of the Institute of Electronics, Information and Communication Engineers (IEICE), vol.96, no.2, pp.95-99, February 2013. (in Japanese)
• T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2012), Aug. 2012.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E94-A, no.12, pp.2545-2553, Dec. 2011.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2011), pp.189-194, Sept. 2011.
• Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Application Design of Multi-Standard Decoder on Media-Centric Reconfigurable Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition), vol.J93-A, no.6, pp.397-413, June 2010.
• H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration," in Proceedings of International Symposium on Quality Electronic Design (ISQED 2010), pp.646-651, Mar. 2010.
• D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2009), pp.186-192, Sept. 2009.
• Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Area-Efficient Reconfigurable Architecture for Media Processing," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp.3651-3662, Dec. 2008.
• Y. Mitsuyama, M. Kimura, T. Onoye, I. Shirakawa, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp.899-906, April 2005.
• Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Embedded Architecture of IEEE802.11i Cipher Algorithms," in Proceedings of IEEE International Symposium on Consumer Electronics (ISCE 2004) , pp. 241-246, Sept. 2004. (Best Paper Award)
• Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "Burst Mode, A New Acceleration Mode for 128-bit Block Ciphers," in Proceedings of Custom Integrated Circuits Conference (CICC 2002), pp. 151-154, May 2002.
• Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfiguration Hardware-Based Cipher,'' IPSJ Journal, vol. 42, no. 4, pp. 958-966, April 2001.
• Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem," Symposium on VLSI Circuits Digest of Technical Papers, pp. 204-205, June 2000.

Academic Degree:

• Ph.D. Information Science and Technology, Osaka University, 2010
• M.Eng. Information Systems Engineering, Osaka University, 2000
• B.Eng. Information Systems Engineering, Osaka University, 1998

Professional Societies:

• Member, Institute of Electrical and Electronics Engineers (IEEE)
• Member, Institute of Electronics, Information and Communication Engineers (IEICE)
• Member, Information Processing Society of Japan (IPSJ)

Professional Activities:

• Committee Member (2024-2025), IEEE Japan Council History Committee
• Chair (2025-2026), IEEE Shikoku Section
• Vice Chair (2023-2024), IEEE Shikoku Section
• Professional Activities Chair (2021-2022), IEEE Shikoku Section
• Finance Chair (2020), IEEE Resigon 10 Conference (TENCON)
• ASP-DAC Liaison at ACM SIGDA Student Research Forum (2021), Asia and South Pacific Design Automation Conference (ASP-DAC)
• Finance Chair (2018), International Conference on Field-Programmable Technology (ICFPT)
• Director (2016, 2017), IEICE Transactions on Fundamentals, Japanese Edition
• Director (2015, 2016), FInance, IEICE Shikoku Section
• Associate Editors-in-Chief (2017, 2018), IPSJ Transactions on System LSI Design Methodology
• Guest Editor (2017), IEICE Transactions on Fundamentals, Special Section on "VLSI Design and CAD Algorithm"
• Guest Associate Editor (2018, 2019, 2020), IEICE Transactions on Fundamentals, Special Section on "VLSI Design and CAD Algorithm"
• Guest Associate Editor (2020), IEICE Transactions on Fundamentals, Special Section on "Circuits and Systems"
• Guest Associate Editor (2012, 2013, 2015, 2018, 2019), IEICE Transactions on Information and Systems, Special Section on "Reconfigurable Systems"
• Registration Chair (2016), Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
• Registration Chair (2013), International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
• Publicity Chair (2012), International Conference on Embedded Systems and Intelligent Technology (ICESIT)
• Track Co-Chair of "VLSI, Circuits and Systems" (2015) , Program Committee, International Symposium on Communications and Information Technologies (ISCIT)
• Program Committee Member (2013, 2014, 2018, 2019), International Conference on Field-Programmable Technology (ICFPT)
• Technical Program Committee Member (2025), Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
• Program Committee Member (2013, 2014, 2015, 2016, 2017, 2018), International Workshop on Computer Systems and Architectures (CSA)